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    Archived pages: 23 . Archive date: 2014-08.

  • Title: Home: E-nvm
    Descriptive info: .. header.. Home.. Presentation.. Objectives.. Committee.. Conference venue.. How to go to the event?.. Accommodation.. Programme.. Speakers.. Posters.. Sponsorship.. Exhibition.. Registration.. Contact.. You are here :.. E-nvm.. Welcome to the Leading Edge Embedded NVM Workshop website.. For its 2nd edition, the e-NVM conference organized by ARCSIS with the support of the ENSM-SE, was very successful and was unanimously appreciated by the attendees.. Indeed, more than 180 persons were present from September 30th to October 1st at the CMP in Gardanne.. Coming from 13 different countries (Belgium, China, France, Germany, Italy, Liechtenstein, Singapore, South Korea, Switzerland, Netherlands, the United Kingdom, Ukraine and the United States), the attendees were able to discover the last technological breakthroughs in the domain.. You will find all the photos.. here.. The Leading Edge Embedded NVM Workshop (e-NVM).. ,.. with the support of l'Ecole Nationale Supérieur des Mines de Saint-Etienne , is organized by.. ARCSIS.. , a trade association for the microelectronics and semiconductor activities in the Provence-Alpes-Riviera (PACA) region, in France.. ARCSIS participates in assuring sustainability, full economic development and enhanced competitiveness of the regional microelectronics and communicating objects industry.. Further to the success of the first edition of the e-NVM workshop in 2011 with over 160 international participants, ARCSIS reiterates the event in 2013.. The second edition will take place on September 30 October 1, 2013 at the Centre Microélectronique de Provence in Gardanne (Southern France).. The.. e-NVM Workshop.. aims to bring together researchers and industrials of  ...   KONG.. IEF -.. Damien QUERLIOZ.. IM2NP, Aix-Marseille University -.. Marc BOCQUET.. Infineon Technologies.. - Christian PETERS.. IRCGN.. - Lieutenant Matthieu REGNERY.. LFoundry.. - Isabelle CONSTANT.. Micron -.. Roberto BEZ.. Nantero.. - Thomas RUECKES.. NXP -.. Tom WILLE.. Oerlikon.. - Mohamed ELGHAZZALI.. Projet MARS, LIRMM -.. Lionel TORRES.. Rambus.. - Christophe CHEVALLIER.. SST-Microchip -.. Alex KOTOV.. STMicroelectronics.. - Alfonso MAURELLI.. - Paola ZULIANI.. University of Modena.. - Andrea PADOVANI.. The workshop will cover themes dedicated to embarked nonvolatile memories, during a two-day conference programme, through 4 sessions :.. Embedded flash memories technology providers: state of the art and trends.. Emerging and leading-edge technologies for Non Volatile Memories (PCM, RRAM and others).. Device and architectures.. Users, Applications and Security.. Who should attend:.. fundamental and applied researchers,.. engineers from design, test, manufacturing, applications areas,.. marketing, sales business development managers,.. technology developers,.. Attendees.. are given the o.. pportunity.. to expose a poster or.. promote their company via a table top in the exhibition aera of e-NVM.. If you are interested in exposing a poster, please send us a 10-line abstract, including title, authors, and company/institution names.. If you are interested in having a table top, please contact us as soon as possible.. Information and registration :.. Corinne Joachim.. , marketing manager /.. Charlène Froment.. , marketing assistant:.. contact[at sign]e-nvm.. org.. Event supported by:.. Sponsored by:.. Identification.. Username:.. Password:.. Copyright © 2012 Leading Edge Embedded NVM.. DESIGNED BY: AS DESIGNING.. Terms of use.. Site map.. PimentRouge.. fr..

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  • Title: Home: E-nvm
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  • Title: Presentation: E-nvm
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  • Title: Objectives: E-nvm
    Descriptive info: Currently, the microelectronics industry faces new technological challenges requiring constant improvements in the performances of memory devices in terms of access time, storage capacity, endurance or data retention.. The main issues to overcome are the downsizing of the memory cell necessary to embed an increasing number of elementary devices and the fulfillment of increasingly aggressive specifications from applications.. Beside Flash technologies, opportunities are opened for alternative storage  ...   to satisfy the growing need for storage capacity, while complying with drastic applicative specifications (lower power consumption, smaller form factor, longer data retention, zero-defect products.. ).. The aim of.. Leading Egde Embedded NVM Workshop.. is to bring together researchers and industrials of both sides of the chain: designers and manufacturers on the one hand and the contractors and end-users on the other hand, around Embedded non-volatile memories..

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  • Title: Committee: E-nvm
    Descriptive info: Steering Committee.. Philippe BOIVIN.. - STMicroelectronics.. Damien DELERUYELLE.. -.. IM2NP, Aix-Marseille University.. Christian DUPUY.. Starchip.. Luc JEANNEROT.. - ARCSIS.. Yves LEDUC.. - Polytech Sophia, University of Nice.. Didier NEE.. - Inside Secure.. Jean-Michel PORTAL.. - IM2NP, Aix-Marseille University.. Bertrand SAILLET.. - LFoundry.. Didier SAVE.. - Gemalto.. Assia TRIA.. - CEA-EMSE.. Arnaud VIRAZEL.. - LIRMM.. Contact Information.. :.. , Marketing Manager,.. Cindy Pons.. , Marketing Assistant: +33 (4)42 53 81 50.. Mail..

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  • Title: Conference venue: E-nvm
    Descriptive info: This Meeting will be hosted by the Provence Microelectronics Centre in Gardanne, one above the 5 research centers of the “École nationale supérieure des mines de Saint-Étienne, a grande école of engineering”.. It is located at the heart of a major Microelectronics cluster in France gathering leading manufacturers of semiconductor devices and smart cards.. It is also 20 km from Aix en Provence, which is a city of art and culture.. Moreover, it is an ideal base for visiting the rest of Provence.. For further information about Provence:.. www.. visitprovence.. com.. Centre Microélectronique de Provence (CMP) Georges Charpak.. 880, avenue de Mimet 13120 Gardanne, France.. About the École nationale supérieure des mines  ...   has been nurtured for nearly two centuries through its exploration of new scientific themes and international partnerships, which makes it a unique player among the top 15 French “Grandes Ecoles d’Ingénieurs”.. ENSM-SE provides students and young researchers with an optimal learning environment and offers a wide range of graduate and post-graduate courses in fields of research as varied as materials sciences, microelectronics, biomedical engineering, IT, environmental and industrial engineering.. The school’s expertise is based on innovative teaching methods combining lectures and individual and group project work carried out in a corporate context.. Strong industry relationships, research inspired learning and state-of-the-art equipment constantly foster innovative projects in education and research.. More information :.. emse..

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  • Title: How to go to the event?: E-nvm
    Descriptive info: The conference will take place at the Ecole Nationale Supérieure des Mines de Saint-Etienne, Centre Microélectronique de Provence Georges Charpak in Gardanne (Southern France, next to Aix-en-Provence).. International Airport « Marseille-Provence » : 30km from Aix-en-Provence city center.. High Speed Train station (TGV): 20km from Aix-en-Provence city center.. 3h from Paris by High Speed Train (Aix-en-Provence TGV station).. 100km from the French Riviera (Nice, Cannes, Saint-Tropez, Monaco).. 35km from Marseille (second largest city in France).. Address:.. Ecole Nationale des Mines de Saint-Etienne.. Centre Microélectronique de Provence.. Campus Georges Charpak.. 880, route de Mimet.. 13120 Gardanne (France).. GPS coordinates: 43°26.. 7073 N / 5° 28.. 7874E.. If you come from Marseille-Provence Airport (30km from Aix-en-Provence city center, 45km from  ...   in the city centre and take a train for Gardanne.. If you come from the Aix-en-Provence High Speed Train Station (TGV station), you have two possibilities to go to Gardanne:.. Take a taxi (around 30 minutes – 40-50 €).. The railway station is in the Centre of Aix-en-Provence (5 min walking from the famous fountain “La Rotonde”).. For railway timetables, please click.. Y.. ou have to look at the train trip from.. Gardanne to Aix-en-Provence (first page).. or/and from.. Aix-en-Provence to Gardanne (second page).. Do not forget to.. check the following information (above timetables):.. Sauf.. sam, dim et fériés (excepted Saturdays, Sundays and bank holidays.. ).. Sauf dim et fériés (excepted Sundays and bank holidays).. Tous les jours (everyday)..

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  • Title: Accommodation: E-nvm
    Descriptive info: The tourism office of Aix-en-Provence is in charge of pre-book hotel rooms in the town (with preferential tariff) in order to insure your hotel reservation.. To book an hotel room, please download the.. hotel booking form.. You have.. until August 14.. th.. 2013.. to send it back to the tourism office of Aix-en-Provence.. After this date preferential tariff and availabilities are not guaranted.. To have a  ...   2 minutes walking from the hotels.. Cézanne.. and.. Le Saint-Christophe.. , 10 minutes walking from the hotel.. La Rotonde.. and 15 minutes walking from the hotel.. Le Mozart.. -----------------------------------------------------------------------------------.. If you need any information about the Aix-en-Provence hotels, please get in contact with the Hotel Booking Service:.. CONTACTS.. :.. Fabienne MORUCCI, Tanja BACHER Florence THURET.. Congress Department.. Tel: 00 33 (0)4 42 16 10 09.. hotelcongres[@]aixenprovencetourism..

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  • Title: Programme: E-nvm
    Descriptive info: e-NVM programme:.. Monday 30th September 2013.. 8.. 00 am: Registration - Welcome coffee.. 45 am: Workshop opening (ARCSIS and CMP).. 9.. 00 am:.. Keynote speaker,.. Jean DEVIN.. , STMicroelectronics.. , France.. Session 1 - Part 1: Embedded flash memories Technology providers: state of the art and trends.. Chairpersons:.. Christian DUPUY (StarChip), Philippe BOIVIN (STMicroelectronics).. 30 am: The Scalability of the Split-Gate NOR Flash for future SoC applications.. Grace Semiconductor Manufacturing Corporation.. , China.. 55 am: Application and cost-down requirements for next generation embedded non-volatile memories.. Dr.. Thomas Wille.. NXP Semiconductors.. , Germany.. 10.. 20 am: Challenges of embedded NVM in the automotive field.. Alfonso MAURELLI.. , Italy.. 45 am: Break.. Session 2 - Part 1: Emerging and leading-edge technologies for Non-Volatile Memories: PCM.. Didier SAVE (Gemalto), Bertrand SAILLET (LFoundry).. 11.. 10 am: PCM Role in the Memory Technology Evolution.. 35 am: Scaling challenges for MOS-selected Phase Change Memory.. Paola ZULIANI.. , STMicroelectronics,.. Italy.. 12.. 00 pm: Advanced thin film technology for NVM development and pilot production.. Mohamed ELGHAZZALI.. , Liechtenstein.. 25 pm: Lunch / Poster session.. Session 2 - Part 2: Emerging and leading-edge technologies for Non Volatile Memories: RRAM.. 2.. 00 pm: RRAM as an Embedded NVM Technology.. Christophe CHEVALLIER,.. , USA.. 25 pm: Innovative materials precoding methods to address the packaging thermal issue in RRAM.. CEA-Leti.. 50 pm: ASM ALD Solutions: Taking Memory to the next Level.. Robin ROELOFS.. ASM.. 3.. 15 pm Break.. Session 2 - Part 3: Emerging and leading-edge technologies for Non Volatile Memories: RRAM and others.. Yves LEDUC (Polytech Sophia,  ...   Aspects - Program Disturb.. SST-Microchip.. 45 am: Development of embedded flash in 65nm for automotive, industrial and consumer products.. Christian PETERS.. 10 am: Break.. Session 2 - Part 4: Emerging and leading-edge technologies for Non-Volatiles Memories: RRAM and others.. of Nice), Damien DELERUYELLE (IM2NP, Aix-Marseille Univ.. 35 am: Printed Technologies at CEA Liten: Apllications to Non Volatile Memories on Flexible Substrate.. Romain COPPARD.. 00 am: “Materials and Integration of e-NVM: Classic and New Approaches”.. Er-Xuang PING.. Applied Materials.. Session 3 - Part 1: Device and architectures.. Jean-Michel PORTAL (.. IM2NP, Aix-Marseille Univ.. ), Arnaud VIRAZEL (LIRMM).. 25 am: Understanding operation and reliability of Hf-based RRAM Devices Through a Microscopic, Material Related Physical Model.. Andrea PADOVANI.. Modena University.. 50 am: Emerging Resistive Memories: Compact Models.. IM2NP.. , France.. 15 pm: Design Exploration of Hybrid ICs using CMOS and ReRAM Technologies.. 40 pm: Lunch / Poster Session.. Session 3 - Part 2: Device and architectures.. 00 pm: Magnetic Memory and embedded processors.. LIRMM - Projet MARS.. 25 pm: Testing and Tolerating Faults in TAS-MRAMs.. Valentin GHERMAN/Joao AZEVEDO.. 50 pm: Non-Volatile memories: a breakthrough for cognitive computing.. IEF.. 15 pm: Break.. Session 4: Users, applications and security.. Assia TRIA (CEA-EMSE), Didier NEE (Inside Secure).. 40 pm: Looking for low power, fast and cost efficient e-NVM for digital security.. Pascal LEROY.. 05 pm: True and false ideas about the eligibility of leading edge NVM technologies for automotive applications.. Hugues RAYNAL.. 30 pm: Recovery data from flash memories.. Lieutenant Matthieu REGNERY.. 55 pm: End of the day.. 5.. 00 pm: Conference closure..

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  • Title: Speakers: E-nvm
    Descriptive info: Jean DEVIN, STMicroelectronics.. Jean Devin (STMicroelectronics Rousset) is currently R D director for the Microcontrollers, Memories Smartc.. His speech.. A Quiz about Embedded NVM today ‘s challenges - e-NVM field is enjoying an exciting period where.. Jean Devin (STMicroelectronics Rousset) is currently R D director for the Microcontrollers, Memories Smartcards (MMS) Group within STMicroelectronics, He graduated in Electronic Engineering from the Ecole Supérieure d’Ingénieurs en Electronique et Electrotechnique (ESIEE) in Paris.. Within the MMS group, he has the major responsibility for technologies, especially embedded NVM, definition and choices.. He is also managing the overall MMS group embedded NVM development team (45 persons) split between France and Italy.. Since 1983, he has been always involved in design and development of NVM circuits, initially EPROM, and the FLAH and EEPROM.. He is author or co-author of many papers in that field and held more than 35 patents to NVM circuits and usages.. A Quiz about Embedded NVM today ‘s challenges.. - e-NVM field is enjoying an exciting period where many innovative concepts for cell storage are driving large R D activities and are announced for next product generations by some key players in this area.. Through some very simple open questions, we will try to guess how those evolutions could materialize and bring added value for suppliers customers.. Alexander KOTOV, SST-Microchip.. Mr.. Alexander Kotov has over 30 years of experience working in the area of Flash, EEPROM, CDD and CMOS technology development.. Three Generations of SuperFlash Split Gate Cell: Scaling Aspects - Program Disturb - I.. He worked for a number of research institutes and semiconductor companies in Ukraine and Russia from 1981 to 1998 and focused on embedded technology development, testing and reliability.. Since 1998, he has been with SST, supervising Device and Reliability Physics Group and he is currently Technical Fellow leading Embedded Technology R D.. Kotov holds 16 U.. S.. and international patents and has published 12 technical papers.. His research interests include NVM solutions for safety critical automotive, mobile and low power consumer applications.. Kotov received MS degree in Semiconductor Physics from Moscow Institute of Physics and Technology in 1981.. Three Generations of SuperFlash Split Gate Cell: Scaling Aspects - Program Disturb.. - In this talk we overwiev basic program disturb mechanisms observed in various flash memory devices based on hot electron injection programming mechanism in the light of embedded memory market requirements.. Three generations of Embedded SuperFlash (ESF) technology are presented with focus on program disturb (PD) mechanisms and their implication on technology scaling.. The latest ESF3 cell generation has scalable thin select gate oxide and utilizes coupling gate assisted highly-efficient programming.. These distinctive features make ESF3 technology scaling down to 40 nm and beyond.. Good quality of Si-SiO.. interface in the cell channel area (Nit 3.. 10.. cm.. -2.. ) ensures PD immunity over automotive operating temperature range up to +175°C.. Joao AZEVEDO, LIRMM.. He worked several years as Hardware design Engineer and Digital IC design Engineer for telecommunication devices and RFID tags.. He received his B.. Sc.. Testing and Tolerating Faults in TAS-MRAMs - Consumer applications like digital audio players and tablet P.. in Computer Engineering and M.. in Microelectronics degrees from the Federal University of Rio Grande do Sul, Porto Alegre, Brazil.. He is currently a Ph.. D.. candidate at LIRMM, Montpellier, France.. His current research subject interests include Test and Reliability of MRAMs and related design issues in VLSI.. Testing and Tolerating Faults in TAS-MRAMs.. - Consumer applications like digital audio players and tablet PCs require more and more integration of non-volatile embedded memories.. Though widely used, non-volatile Flash memories still have several drawbacks such as high supply voltage requirement and susceptibility to reliability issues due to high electric field for programming operations.. MRAMs have the potential to mitigate almost all Flash related issues.. However, they are prone to manufacturing defects and reliability threats as any other kind of memory.. Only few papers on MRAM testing or MRAM fault tolerance can be found in the literature, and target mainly FIMS-MRAMs technologies.. A thorough investigation and deep analysis must be done for testing MRAMs memories.. An analysis of resistive-open defects in TAS-MRAM memory architecture is presented.. This study has revealed the importance of electrical analyses of defects related to magnetic fabrication process and memory architecture that may impact the functionality of TAS-MRAMs.. Fault-tolerance schemes for MRAM memories are also proposed.. These schemes target specific reliability threats that manifest as erasures, i.. e.. errors with known location but unknown value.. For example, a dielectric breakdown may reduce the electrical resistance of an MRAM cell sensibly below the levels which correspond to logic 0 and logic 1 values stored in healthy MRAM cells.. Such deviations can be sensed during memory read operations and the acquired information can be used to boost the error-correction capability of an error-correcting code.. Here, the erasure information is used to enable double-bit error correction with the help of single-bit error correction and double-bit error detection codes or shortened single-bit error correction codes.. Roberto BEZ, Micron.. Roberto Bez graduated in Physics from the University of Milan (Italy) in 1985.. In 1987 he joined the Central R D Department of STMicroelectronics.. PCM Role in the Memory Technology Evolution - Phase Change Memory (PCM) is a Non-Volatile Memory (NVM) technolo.. In 1987 he joined the Central R D Department of STMicroelectronics and started to work on nonvolatile memory (NVM) technologies.. In the 1990s, he participated in the development of the NOR Flash memory technology, initially as expert of the device physics and reliability and subsequently as Project Leader of the multilevel product development.. Since 2001 he has been working on the development of the NAND Flash memory and on the emerging technology based on the phase change memory (PCM) concept.. In March 2008 he joined Numonyx, driving the development of the PCM and other alternative NVM technology.. From April 2010 he is with the Process R D of Micron.. He has authored numerous papers, conference contributions, and patents on topics related to NVM.. He has been lecturer on Electron Device Physics at the University of Milan and in Non-Volatile Memory Devices at the University of Padova, Politecnico of Milan, and University of Udine.. PCM Role in the Memory Technology Evolution.. - Phase Change Memory (PCM) is a Non-Volatile Memory (NVM) technology that provides a set of features interesting for new applications, combining features of NVM and DRAM.. PCM is at the same time a sustaining and a disruptive technology.. From application point of view, PCM can be exploited by all the memory systems, especially the ones resulting from the convergence of consumer, computer and communication electronics.. The key functional features combined with data retention, single bit alterability, execution in place and good cycling performance enables traditional NVM utilizations but also already opened applications in LPDDR filed.. Moreover PCM is considered the essential ingredient to push to the market the so called Storage-Class Memory (SCM), a non-volatile solid-state memory technology that is capable of fill the gap between CPU and disks.. In order to be able to enter into a well established stand-alone memory market there are key factors that must be fulfilled: i) match the cost of the existing technology in terms of cell size and process complexity, ii) find application opportunities optimizing the overall “memory system” and iii) provide a good perspective in terms of scalability.. Phase Change Memory has been able so far to progress in line with all these requirements.. Aim of this presentation is to review the PCM technology status and to discuss specific opportunities for PCM to enter in the broad memory market.. Marc BOCQUET, IM2NP, Aix-Marseille University.. Marc Bocquet obtained respectively his Master and PhD degree in 2006 and 2009 from University Grenoble.. In 2010, he becomes a.. Emerging Resistive Memories: Compact Models - Memory devices based on switching materi.. In 2010, he becomes an associate professor at the University of Marseille, Polytech'Marseille (Microelectronic) and he is member of the memories Team , IM2NP.. He has significant experience in th field of electrical characterization and device modeling.. He has conducted several studies on understanding the physical mechanisms in dielectrics to link the physical and chemical properties to the electrical performance/reliability of memory devices: flash and resistive memory.. Emerging Resistive Memories: Compact Models.. - Memory devices based on switching materials are currently pointed out as promising candidates to replace conventional non-volatile memory devices beyond 2xnm-technological nodes.. But to fully explore new design concepts such as distributed memory in logic, RRAM compact models have to be developed and inserted in lectrical simulators, at a circuit level.. The main goal of this presentation is to present RRAM compact models.. After a state of the art of the RRAM physical model, compact models are presented.. These models exhibit electrical behaviors in good agreement with quasi-static and dynamic experimental data.. Christophe CHEVALLIER, Rambus.. Christophe Chevallier is VP of Product Development in the NVM/Storage division of Rambus.. He was a co-founder of Unity Semico.. RRAM as an Embedded NVM Technology - In this presentation we will review Resistive Mem.. He was a co-founder of Unity Semiconductor, acquired by Rambus.. He joined Unity to develop stacked cross-point arrays architectures and RRAM technologies.. He designed one of the world's first low voltage NOR Flash at Catalyst Semiconductor, and later help start Micron Technology's Flash business.. Earlier, Christophe was a key memory designer at AMD and STMicroelectronics.. Chevallier holds two hundred patents.. He graduated from Ecole Centrale de Marseille, France, and with an MS in Electrical Engineering from Stanford University.. RRAM as an Embedded NVM Technology.. - In this presentation we will review Resistive Memory (RRAM) developments and how they apply to embedded NVM applications.. We will compare RRAM to existing technologies and highlight applications particularly suited to RRAM specifications.. Density, read and write speed, endurance and data retention as well as overall reliability will be studied.. Manufacturing and test costs will also be considered.. A road map for RRAM development will be proposed.. Isabelle CONSTANT, LFoundry.. Currently director of the R D-technology development department in LFoundry Rousset site, I was previously project direct.. Her speech.. Leading performances and competitiveness for embedded security: how to get both? -&nbs.. Currently director of the R D-technology development department in LFoundry Rousset site, I was previously project director in PValliance for photovoltaic area.. My background is essentially related semiconductor within several entities from start up, international industries academic, covering topics from device manufacturing to product development; I have a PhD in physics.. Leading performances and competitiveness for embedded security: how to get both?.. - In a fast moving market such as security, it is important to keep a leadership on technical performances and at the same time to ensure price competitiveness.. It is raising questions about which type of process can be used to optimize the benefit of innovative technologies: mature or advanced process? Innovating technologies such as asynchronous technology or low power flash, which are ported on a mature node such as 110nm Aluminium, could be the perfect combination.. The purpose of the presentation is to analyse the effectiveness of technology innovation developed on mature process.. Romain COPPARD, CEA Liten.. Romain Coppard (53) obtained a PhD degree in Semiconductor Device Physics in 1984.. He has been working in the field of Organi.. Printed Technologies at CEA Liten: Applications to Non Volatile Memories on Flexible Substrate.. He has been working in the field of Organic Electronics since 2007, and held before various positions at major Silicon Microelectronics Companies (Alcatel, Applied Materials, ATMEL).. He is currently heading the Laboratory of Printed Electronics Devices in CEA Liten (Grenoble-France), developing Technologies on Flexible Substrate for Transistors, Sensors and Non Volatile memories.. He holds 5 patents and co-authored more than 50 papers.. - Different electronic devices can be processed on flexible substrate using printing techniques.. Among these devices, CEA Liten is currently active on Printed Non Volatile Memories, that could address various markets, such as Packaging, RFID tags, and even Sensors.. But a full NVM system requires on top of the NVM memory cell other components: circuits for memory row selection, circuits for memory sensing.. These circuits can also be designed and processed using CMOS printed technologies.. In our talk, we will present our latest results on printed OTFT technologies and their recent demonstrations for digital or analog applications.. We will detail the current activities running with IM2NP Marseille, to design and simulate peripheric circuit, as well as outline the performanes obtained from CEA printed ferroelectric memories using PVDF-TrFE co-polymers supplied by ARKEMA company.. Mohamed ELGHAZZALI, OERLIKON Systems/R&D.. Mohamed Elghazzali obtained his Diploma on material of science at Nürnberg/German.. “Advanced thin film technology for NVM development and pilot p.. Mohamed Elghazzali obtained his Diploma on material of science at Nürnberg/Germany in 1998.. He worked 2 years for Ceramics and Glass industries and developed new furnace for fiber glass.. He has joined UNAXIS 2000 and get involved to install and develop PVD systems and processes.. He starts developing NVM sputtering techniques and hardware since 2002.. He works for R D team of OC Oerlikon since 2006 as senior process engineer.. His focus now is on highly ionized sputtering to fill high aspect ratio features for TSV (through-silicon-via) technology.. “Advanced thin film technology for NVM development and pilot production” -.. The development and pilot production of phase change memory materials and devices requires PVD hardware being very flexible and robust, but also close to the production solution.. This hardware has been developed for the Clusterline® and includes dedicated preheat and degas stations, an ICP etch module, regular and medium throw PVD modules as well as multi target sputter stations with rotating substrates, called the Multi-Source cathode (MSQ).. All these solutions have been fully integrated on the Clusterline® platform on 200 and 300mm substrates.. The PVD module provides DC or DC pulsed deposition at variable target substrate distance with RF Bias and heatable substrate.. The MSQ enables co-sputtering as well as the deposition of multilayers from up to 4 targets, which can be configured as magnetron sputtering DC, DC pulsed or RF sources.. By this a variety of NVM material compositions can be produced from less and cheaper targets including insulating materials – a huge  ...   film group manager.. He holds 152 issued patents in the area of semiconductor memory.. “Materials and Integration of e-NVM: Classic and New Approaches.. ”- We will discuss various emerging NVM technologies that will power the advanced semiconductors that are facing scaling limits from existing NVM technologies such as NAND and NOR.. Highlighting the device, integration and manufacturing challenges ahead as transition to new NVM technologies, the discussion will focus on required material changes, the increased integration and manufacturing complexity, and the innovation to address these challenges.. The equipment and techniques which enable highly controlled material interfaces and atomically precise thin film processing that are required in manufacturing will be discussed.. Damien QUERLIOZ, Institut d'Electronique Fondamentale.. Damien Querlioz received his pre-doctoral training at ecole Normale Supérieure Paris and graduated the Ph.. from Universit.. Non-Volatile memories: a breakthrough for cognitive computing - Novel nonvolatile tech.. from University Paris-Sud in 2008.. He was a postdoctoral scholar at Stanford University in 2009 and at CEA LIST in 2010.. In 2010, he joined Institut d'Electronique Fondamentale as a tenured CNRS researcher to develop new concepts in nanoelectronics relying on novel non-volatile memories and bioinspiration.. With Philippe Dollfus, he is the co-author of the book: The Wigner Monte-Carlo Method for Nanoelectronic Devices (ISTE/Wiley).. He is serving as expert for the French Observatory of Micro and Nano Technologies.. Non-Volatile memories: a breakthrough for cognitive computing.. - Novel nonvolatile technologies are a radical innovation for the memory market.. They can also constitute a breakthrough for novel forms of bioinspired, low-power computing.. Nonvolatile memories used as synapses can indeed be the core technology of ultra-adaptable systems for cognitive-type applications.. In this talk, I will present how phase change, resistive and magnetic memories may be used in that context.. System-level simulation show the applications which may be achieved.. Detailed discussion on the impact of memories' properties highlight significant differences with traditional memory applications.. Hugues RAYNAL, Continental.. Hugues Raynal obtained his diploma of Engineer in Electronics in 1988.. from Engineering School ENSEEIHT in Toulouse.. He has 23 years of experienc.. True and false ideas about the eligibility of leading edge NVM technologies for automotive applications -&.. He has 23 years of experience in automotive electronics, starting in 1990 at Siemens Automotive, now Continental.. He has occupied various positions in Design (real time software and new products architecture), followed by 3 years in Supply Chain, and since 2000 in Supplier Quality Management.. Since 2004, he is Quality Manager responsible for the Memories purchased by Continental.. This encompasses the evaluation and qualification of new suppliers and technologies according to Continental's Quality requirements.. True and false ideas about the eligibility of leading edge NVM technologies for automotive applications.. - Electronics has become crucial to make mobility and transport sustainable, with environmental friendly, safer, more comfortable, more individual and affordable vehicles.. Consequently NVMs used in Continental products are increasing in diversity and complexity, while keeping up with the cost reduction pace.. The eligibility of NVM leading edge technologies is a crucial challenge for automotive applications.. ”.. Matthieu REGNERY, Institut de Recherche Criminelle de la Gendarmerie Nationale.. Matthieu Regnery obtained is Master degree in 2008.. Then he followed a two years military training to become a member of the French Gendarmerie.. He is.. Recovering data from flash memories: - With the development of high tech devices, cruc.. He is currently working as a forensic specialist at the French Gendarmerie national forensic institute.. He is focused on data extraction, from any kind of digital device.. The different cases he has to investigate always involve NVM.. He is mostly working on protected or malfunctionning hard drives and flash components.. Recovering data from flash memories.. : - With the development of high tech devices, crucial investigations evidences are often hold by NVM.. Gaining access to this data can be tough.. Indeed, devices as well as their memories may be locked or damaged (water, fire, …).. Also the data may have been erased by the user but still present.. Thus, one of the challenges is to be able to read bare memory, bypassing the controller if needed.. Researches on eMMC chips and SSDs are currently conducted in this way.. A second challenge is to reverse the flash management layer in order to get useable data.. Robin ROELOFS, MSc, ASM International (Corporate R&D).. Robin Roelofs (age 25), received the M.. in applied physics from Eindhoven University of Technology (The Netherlands).. He graduated in the Plasma &a.. ASM ALD Solutions: Taking Memory to the next level - Next generation memory devices set challenging r.. He graduated in the Plasma Materials Processing group on the topic of Energy-Enhanced ALD for Spacer Defined Double Patterning.. Directly after his graduation he joined ASM International, as a process engineer for Corporate R D located at ASM Belgium.. Currently, he is involved in a wide range of R D activities, including novel metal (gate) materials and the development ReRAM solutions.. ASM ALD Solutions: Taking Memory to the next level.. - Next generation memory devices set challenging requirements in terms of material quality and 3D integration.. One attractive approach for NVM application is oxide based ReRAM, where good quality high-K ALD films are required in order to obtain promising figures on switching speed, endurance and retention.. Performance can be further enhanced by tuning film composition using doped and/or mixed oxides.. ALD can handle these strict material requirements even in 3D integration.. Our HVM compatible ALD reactor designs with innovative precursor delivery systems can therefore help taking memory solutions to the next level.. Thomas RUECKES, Nantero.. Thomas Rueckes is Co-founder and Chief Technology Officer of Nantero where he oversees carbon nanotube chemistry, process int.. Advances in Carbon Nanotube Memory (NRAM) - Carbon Nanotube (CNT) films exhibit resist.. Thomas Rueckes is Co-founder and Chief Technology Officer of Nantero where he oversees carbon nanotube chemistry, process integration, circuit design and testing activities.. He is the inventor of the NRAM.. TM.. carbon nanotube memory device and co-founded Nantero to commercialize this invention in 2001.. He is inventor on 163 granted patents with more than 160 patents pending and earned his Ph.. in Chemistry from Havard University in 2001.. Advances in Carbon Nanotube Memory (NRAM).. - Carbon Nanotube (CNT) films exhibit resistance change behavior suitable for semiconductor memories at CMOS-compatible voltages and currents, high endurance, electrical device uniformity, excellent data retention and read/write disturb immunity combined with a simple fabrication process.. Using top-down integration of a wafer-scale uniform CNT film sandwiched between electrodes, high yielding multi-Mbit CNT memory (NRAM) product chips have been fabricated in a standard CMOS process.. Latest device and CNT materials advances will be discussed as well as specific semiconductor memory applications.. Danny SHUM, GlobalFoundries.. Danny Shum is at GLOBALFOUNDRIES as a Fellow TD in NVM Integration.. He is responsible for all NVM related technologiesdevelopment and roadmap.. Pri.. Foundries Model in Leading Edge eNVM with broad portfolio for increasing market demands - Much of GLOBALFOUNDRI.. Prior joining GLOBALFOUNDRIES, he held research position at Texas Instruments (1989–1992) on device design, integration, simulation of EPROM and Flash; Motorola (1992–1998) research and management position on embedded NVM;Infineon (1999-2012) in East Fishkill as Project Manager for various alliance developments, including eNVM and eDRAM, 65/45-nm logic module process.. He has more than 30 patents granted, and has published 50+ technical papers, conference proceedings, and invited talks in the fields of superconductivity, Low temp physics, magnetic properties of transition metal rare earth complexes, eNVM and eDRAM.. Foundries Model in Leading Edge eNVM with broad portfolio for increasing market demands.. - Much of GLOBALFOUNDRIES' eNVM uniqueness lies on the full logic capability in modular approach.. This permits the NVM process shared the core devices, reusability of the baseline design enablement (IP), resulting in process simplicity with faster cycle time.. Built on a mature, robust baseline platform and production-proven technologies in high-volume manufacturing for consumer products, this translates directly to an unprecedented combination of performance and minimal cost of ownership.. Another advantage of full logic compatibility is enable integration with RF CMOS and high voltage to achieve a true system-on-chip (SoC) design to support broad market demands.. Olivier THOMAS, CEA-LETI.. Olivier Thomas received his Ph.. in Electrical Engineering from EDITE, Paris, France in 2004.. He joined the CEA-LETI.. Design Exploration of Hybrid ICs using.. He joined the CEA-LETI Laboratory in the Center for Innovation.. in Micro Nano Technology (MINATEC), Grenoble, France, in 2005.. His research interests include device engineering and technology-circuit co-design using advanced technologies and emerging devices for resilient and energy efficient memory and digital circuit design.. From 2010 to 2012, he was a visiting researcher at Berkeley Wireless Research Center (BWRC) of University of California at Berkeley.. He worked on advanced methodologies to characterize on large-scale static/dynamic SRAM performances.. Currently, he is in charge of the advanced memory design group at LETI.. He is author or co-author of 47 articles in international refereed journals and conferences and 20 patents.. Design Exploration of Hybrid ICs using CMOS and ReRAM technologies -.. In today's wireless devices, many new systems can be specified as normally off.. , instantaneously on.. Among them Smart phone, tablette as well distributed sensor network, smart grids or healfcare monitoring systems are some examples.. They share similar features robustness, resiliency and energy efficiency.. The common limiter in ASIC as well as FPGA is usually the memory.. In this talk we will discuss about memory design, focusing on emerging nonvolatile technologies.. Following a brief introduction on memory design requirements, we will explore the benefits of hybrid CMOS and ReRAM technologies to tackle ICs static power consumption issues while maintaining performances.. Lionel TORRES, LIRMM.. Lionel Torres obtained his MSc in 1993 and his PhD 1996 at the.. “Magnetic Memory and embedded processors”.. Lionel Torres obtained his MSc in 1993 and his PhD 1996 at the University of Montpellier 2.. From 1996 to 1997 he worked for ATMEL as R D engineer.. From 1997 to 2004 he was associate professor at the University of Montpellier 2, Polytech’Montpellier (Microelectronic design) and LIRMM laboratory.. In 2004, he became full Professor and was head of the microelectronics department of LIRMM from 2007 to 2010.. He is now deputy head of the Polytech’Montpellier engineering school.. His research interests and skills concern reconfigurable computing and system level architecture, with specific focus on emerging technologies applications, especially MRAM.. He leads several European, national and industrial projects in this field.. He is involved in major conferences and journals and is (co-)author of more that 150 publications and 9 patents.. - SRAM, DRAM and FLASH have been the three main technologies employed in the design of on-chip processor memories.. However, manufacturing challenges already present in the most advanced nodes compromises this evolution.. MRAM (Magnetic memory) presents itself as an attractive alternative for these technologies, as it has reasonable timing and power characteristics.. Last results described in the state of the art show that MRAM access time is now less than 5ns and read/write energy per bit equivalent to SRAM.. One important feature of MRAM is the non-volatility, allowing to define new instant on/off policies.. In this tallk we propose to show how MRAM can be used into embedded memory hierarchy of embedded systems.. The main objective is to demonstrate the interest to use MRAM for Level-1 2 cache and to better understand the architectural choice in order to minimize the impact of the higher write latency of MRAMs.. One major objective is, for a define application, to keep the same performance, but making significant gains on the energy consumption.. Thomas WILLE, NXP Semiconductors.. Thomas Wille has a degree in applied physics and worked over more than 20 years in various positions within NXP Semiconductors on defining, develo.. Application and cost-down requirements for next generation embedded non-volatile memories - Embedded non-volati.. Thomas Wille has a degree in applied physics and worked over more than 20 years in various positions within NXP Semiconductors on defining, developing and bringing ICs for security application to market.. He is now responsible for the Architecture Technology of NXP’s Business Unit Identification.. Application and cost-down requirements for next generation embedded non-volatile memories.. - Embedded non-volatile memories are used for small applications in the field of industrial, automotive and identification.. In automotive and industrial the main aspect of using embedded non-volatile memory is its flexibility and real time execution performance.. In the field of idenfication market the secure storage of user credentials is the main argument for use of embedded non-volatile memory.. All domains have in common the continous expectation of cost down.. On the other hand the slightly reduction of scaling and the increased required investment for eNV in deep sub-micron technologies make shrinking continously more challenging.. New disruptive eNV technologies promise to solve this increasing dilemma.. Application and scaling requirments of eNV memories will be discussed.. Paola ZULIANI, STMicroelectronics.. Paola Zuliani received the Laurea in Physics from the University of Milan, Italy, in 1993.. In 1997 she joined STMicroelectron.. Scaling challenges for MOS-selected Phase Change Memory - Phase Change Memory is.. In 1997 she joined STMicroelectronics and since then she has been working in the Central R D on the Non Volatile Memory Technology development.. Her activity has been focused on all the aspects concerning technology development for embedded applications based on Floating Gate memories.. Starting from 2007, she is in charge of Phase Change Memory technology development.. She is author of several patents and conference contributions on topics related to NVM.. Scaling challenges for MOS-selected Phase Change Memory.. - Phase Change Memory is the most mature among novel memory concepts.. PCM technology for embedded applications can be a real breakthrough for process cost saving and performances.. The feasibility at 90nm technology node has been solidly proven in an industrial environment and the added value of this solution demonstrated.. So far, MOS selector has been identified as the best choice for embedded Phase Change Memory due to its availability in the standard CMOS platform and low process cost.. In this talk the scaling trend expected for MOS-selected PCM will be discussed, by considering critical parameters for both storage element and selector.. In particular, the trade-off between PCM cell area and selector working point will be considered.. Finally, the scaling of present cell architecture down to 28nm technology node will be proposed..

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  • Title: Posters: E-nvm
    Descriptive info: Posters:.. Determination of physical properties of semiconductor-oxide-semiconductor structures using a new fast gate current measurement protocol.. Philippe Chiquet.. 1.. , Pascal Masson.. , Gilles Micolau.. , Romain Laffont.. , Frederic Lalande.. , Jeremy Postel-Pellerin.. , Arnaud Regnier.. Université d'Aix-Marseille, France - IM2NP;.. Université Nice-Sophia Antipolis, France - IM2NP;.. Université d'Avignon;.. STMicroelectronics.. Resistive switching in the AM4Q8 Mott insulators: from the avalanche breakdown mechanism to Mott memories and memristors.. J.. Tranchant.. , L.. Cario, E.. Janod, B.. Corraze, M.. -P.. Besland.. Institut de Matériaux Jean Rouxel (IMN), Université de Nantes, CNRS, 2 rue de la Houssinière, BP32229, 44322 Nantes, France.. Investigation of resistive memories (RRAM) potentialities – Switching operation and retention performances.. G.. Molas*.. , E.. Vianello, F.. Longnos.. , P.. Blaise, E.. Souchier, C.. Cagli, G.. Palma, J.. Guy, M.. Bernard, M.. Reyboz, A.. Roule, C.. Carabasse, V.. Delaye, V.. Jousseaume, S.. Maitrejean, F.. Dahmani.. Verrier.. , D.. Bretegnier.. , J.. Liebault.. , T.. Cabout, B.. Traore, K.. Xue, L.. Fonseca.. , Y.. Nishi.. Perniola, H.. Grampeix, J.. F.. Nodin, A.. Toffoli, E.. Jalaguier, , O.. Pirrotta.. , A.. Padovani.. Larcher.. , G.. Reimbold, B.. De Salvo.. CEA, LETI, MINATEC, Grenoble, France,.. ALTIS Semiconductor, Corbeil Essonne, France.. DISMI Università di Modena e Reggio Emilia, Reggio Emilia, Italy.. Center  ...   BP 257, 38016 Grenoble Cedex 1.. * LABEX MINOS.. MRAM research @ LIRMM.. Sophiane Senni.. , Joao Azevedo, Lionel Torres, Luis Vitorio Cargnini, Raphael Martins Brum, Bojan Jovanovic, Gilles Sassatelli, Arnaud Virazel, Patrick Girard, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo.. LIRMM – Université Montpellier 2 / CNRS – France.. Dynamic Behavior of Silicon Nanocrystal Memories During the Hot Carrier Injection.. Vincenzo Della Marca.. 1,2, Lia Masoero 1,2, Julien Amouroux2, Julien Delalleau2, Philippe Boivin2 Jean-Luc Ogier2, Gabriel Molas3 ,Jérémy Postel-Pellerin1, Frédéric Lalande1.. 1 IM2NP (UMR CNRS 7334), Technopôle de Château Gombert, 38 rue Frédéric Joliot Curie, 13451 Marseille, France, 2 ST Microelectronics, 190 Avenue Célestin Coq Zone Industrielle, 13106 Rousset, France, 3 CEA-LETI, 17 rue des Martyrs, 38054 Grenoble, France.. A technological and electrical study of Self-Aligned Charge-trap Split-Gate Memory Devices.. C.. Charpin-Nicolle.. de Luca, A.. Persico, G.. Médico, C.. Tallaron, F.. Aussenac, R.. Kies, G.. Molas, L.. Masoero, O.. Cueto, B.. de Salvo.. Multi-level memory cell material based on oxide with graded Al depth profile, such as HfxAl1-xOy.. O.. M.. Orlov1.. Ya.. Krasnikov1, A.. V.. Zablotskiy2, A.. Markeev2, Yu.. Yu.. Lebedinskii2.. 1-Molecular Electronics Research Institute, 124460, 12 -1, 1-st Zapadny lane, Zelenograd, Moscow, Russia; 2-Moscow Institute of Physics and Technology 141700, 9 Institutskii lane, Dolgoprudny, Moscow region, Russia..

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